A programmable logic device, such as an FPGA, receives incoming data from external devices via input/output (I/O) interfaces on the FPGA, processes that data in its logic core, and transmits resulting, outgoing data to the same or other external devices via the same or other I/O interfaces. In some FPGAs, the speed of signaling between the FPGA and external devices is greater than the speed at which the FPGA's logic core operates. As such, such FPGAs are implemented with serializer/deserializer (SERDES) circuits having (i) de-serializers that receive and convert high-speed incoming serial data streams from external devices into lower-speed parallel data streams for processing by the logic core and (ii) serializers that receive and convert resulting lower-speed parallel data streams generated by the logic core into high-speed outgoing serial data streams for transmission to external devices.
Depending on the particular application, the serial data streams to and from an FPGA can have different word sizes (e.g., 4 bit, 7 bits, 8 bits). In order to avoid having to provide different SERDES circuits for each different word size, it is desirable to have the de-serializers and serializers in the FPGA's SERDES circuits be configurable (i.e., programmable) to selectively operate at any one of those different word sizes. For example, an FPGA designed to support any of 4-bit, 7-bit, and 8-bit word sizes should have (i) a de-serializer that can be configured to convert an incoming serial data stream having N-bit words into N parallel data streams and (ii) a serializer that can be configured to convert N resulting parallel data streams into an outgoing serial data stream having N-bit words, where N is any one of 4, 7, and 8. The term “gearing ratio” for a de-serializer or a serializer refers to the ratio between the number of parallel data streams and the single corresponding serial data stream. Thus, a de-serializer that processes N-bit words is said to have a 1:N gearing ratio, while a corresponding serializer is said to have an N:1 gearing ratio.
Traditionally, for de-serializers having odd gearing ratios, such as 1:7, a sampling clock is provided at the same rate as the high-speed incoming serial data stream, where single data rate (SDR) sampling is used to sample the incoming serial data, for example, at each rising edge of the high-speed sampling clock. Similarly, for traditional serializers having odd gearing ratios, such as 7:1, a sampling clock is provided at the same rate as the high-speed outgoing serial data stream, where SDR sampling is used to output another serial data bit, for example, at each rising edge of the high-speed sampling clock.
Another way to achieve a 7:1 odd gearing ratio is to employ a 4:1 even gearing ratio (which can be based on a slower sampling clock than the previously described SDR sampling clock) followed by 4:7 rate-conversion logic. Unfortunately, this extra rate-conversion step consumes a large amount of logic, resulting in both high silicon cost and high power consumption.